Technical Field
The present disclosure relates to a semiconductor device and a semiconductor device manufacturing method.
Related Art
Semiconductor devices in which a semiconductor layer formed with a sensor, and a semiconductor layer formed with a peripheral circuit, are stacked on the same semiconductor substrate with an insulator film interposed therebetween, are known.
Japanese Patent Application Laid-Open (JP-A) No. 2014-135454, for example, describes a semiconductor device including: a photodiode having an n-type second semiconductor layer and a p-type semiconductor region provided above a main face of the second semiconductor layer; a first semiconductor layer provided above the second semiconductor layer and formed with a transistor; a p-type third semiconductor layer provided between the first semiconductor layer and the second semiconductor layer and applied with ground potential; a first insulator layer provided between the first semiconductor layer and the third semiconductor layer; and a second insulator layer provided between the second semiconductor layer and the third semiconductor layer.
JP-A No. 2014-135454 describes how, by fixing the p-type third semiconductor layer to a ground potential, high voltage applied to the second semiconductor layer does not reach the first semiconductor layer, even in a case in which a high voltage is applied to the second semiconductor layer, in order to deplete the second semiconductor layer.
In the semiconductor device described in JP-A No. 2014-135454, when the third semiconductor layer is exposed to plasma in a manufacturing process using plasma, such as etching or CVD, static charges charged in the vicinity of a boundary between the third semiconductor layer and the first insulator layer, and charged in the vicinity of a boundary between the third semiconductor layer and the second insulator layer, retain. Inversion layers are thereby formed inside the third semiconductor layer, at the first insulator layer side and at the second insulator layer side, respectively. In a case in which n-type inversion layers are formed in the third semiconductor layer configured by a p-type semiconductor, the entire third semiconductor layer cannot be fixed to a potential, even in a case in which the third semiconductor layer is applied with the desired potential, and the third semiconductor layer enters an electrically floating state. Thus, in the semiconductor device described in JP-A No. 2014-135454, there may be cases that the third semiconductor layer cannot be fixed to a desired potential, due to inversion layers occurring inside the third semiconductor layer originating from positive charges charged at the periphery of the third semiconductor layer. In a case in which capacitive coupling occurs between the third semiconductor layer in the floating state and the second semiconductor layer applied with a high voltage, a non-illustrated unintentional potential, corresponding to the high voltage applied to the second semiconductor layer, is applied to the third semiconductor layer, and a transistor formed in the first semiconductor layer may erroneously operate due to this influence.